Second Annual Offering: Tutorial on Energy-Secure System Architectures

(ESSA 2012)

 

Held in conjunction with the 2012 International Symposium on Computer Architecture (ISCA-39)

Saturday, June 9, 2012

Portland, Oregon

 


The second annual offering of the Tutorial on Energy-Secure System Architectures (ESSA) is being held in conjunction with ISCA 2012. This tutorial brings together leading experts from academia and industry in exploring the architectural design implications in the late CMOS era. In particular, the power and reliability “walls” have sprung up as major obstacles to achieving historical growth rates in system performance – and this forum deals with the topic of how to build up the science, engineering (and perhaps art) of constructing systems that are energy-secure in the sense that: (a) they are guaranteed to adhere to stipulated energy, power or thermal limits; and, (b) they are immune to maliciously or inadvertently launched program viruses that could disrupt the power management (control) system and cause severe performance or functional damage to the system – if unchecked. This year we plan to have two joint events with the Workshop on Energy Efficient Design (WEED 2012) – the keynote and panel session.

 

FINAL PROGRAM – June 9, 2012

 

8:15 AM

Welcoming Remarks: Pradip Bose and Alper Buyuktosunoglu (Tutorial Organizers)

8:30 AM

ESSA-WEED Joint Keynote: The Future of Computer Architecture: Shekhar Borkar, Intel

9:30 AM

Energy-Secure System Architectures (ESSA) – An Introduction: Pradip Bose, IBM

10:00 – 10:30 AM

Break

10:30 AM

Overcoming Reliability and Complexity Challenges: Subhasish Mitra, Stanford University

11:30 AM

Hierarchical, Multi-core Power Management Protocols: Alper Buyuktosunoglu, IBM

12:00 – 1:30 PM

Lunch

1:30 PM

Guarded, two-level management protocols for safety, security and low verification complexity:  Pradip Bose and Alper Buyuktosunoglu, IBM

2:15 PM

Security-Aware Microarchitectures with Special Emphasis on Software Side Channels: Simha Sethumadhavan, Columbia University

3:15 – 3:30 PM

Break

3:30 PM

Soft Error Modeling of Large Caches in Server Systems: Murali Annavaram, USC

4:30 PM

WEED-ESSA Joint Panel: Cross-stack Energy Optimization - Fact or Fiction?
Panelists – Prof. Todd Austin (U. Michigan), Dr. Shekhar Borkar (Intel), Dr. Pradip Bose (IBM), Dr. Karthick Rajamani (Moderator), Prof. Kevin Skadron (U. Virgina), Prof. Tajana Simunic Rosing (UC San Diego)

 

 

 

Paper References [a representative set of 20] for talks given by Pradip Bose and Alper Buyuktosunoglu

(A full, comprehensive list of paper references covering all the talks will be provided to attendees as part of the Tutorial Notes).

1. P. Bose, A. Buyuktosunoglu, C-Y. Cher, J. A. Darringer, M. S. Gupta, H. Hamann, H. Jacobson, P. N. Kudva, E. Kursun, N. Madan, I. Nair, J. A. Rivers, J. Shin, A. J. Weger, V. Zyuban, “Power-efficient, reliable microprocessor architectures: modeling and design methods,” Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.

2. N.Madan, A. Buyuktosunoglu, P. Bose, M. Annavaram, "A case for guarded power gating in multi-core processors", Proc. 17th Int’l. Symp. on High-Performance Comp. Arch. (HPCA), February 2011

3. D. Brooks and M. Martonosi, “Dynamic thermal management for high-performance microprocessors,” Proc. 7th Int’l. Symp. on High-Performance Comp. Arch. (HPCA), 2001.

4. M. Floyd, M. Ware, K. Rajamani, B. Brock, C. Lefurgy, A. Drake, L. Pesantez, T. Gloekler, J. Tierno, P. Bose, A. Buyuktosunoglu, Introducing the Adaptive Energy Management Features of the POWER7 chip" IEEE MICRO, March 2011.

5. P. Kocher, R. B. Lee, G. McGraw, A. Ranganathan, S. Ravi, “Security as a new dimension in Embedded System Design”, Proc. of 41st. Design Automation Conference (DAC), June 2004; also, Ruby Lee, “Processor Architectures for Efficient Secure Information Processing, 41st. Design Automation Conference invited talks, June 2004.

6. M.K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, B. Abali, "Enhancing Lifetime and Security of Phase Change Memories via Start-Gap Wear Leveling", Proc. of Int'l Symposium on Microarchitecture (MICRO), December 2009.

7. J. Srinivasan, S. A. Adve, P. Bose and J. Rivers, “Lifetime Reliability: Toward an Architectural Solution,IEEE Micro, special issue on Emerging Trends, vol. 25, issue 3, May-June 2005, pp. 2-12.

8. Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston, “A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. 353-362,” Proc. Int’l. Symp. on Computer Architecture (ISCA), June 2008.

9. R. Joseph, D. Brooks and M. Martonosi, “Control techniques to eliminate voltage emergencies in high performance processors,” Proc. Int’l. Symp. on High Performance Comp. Arch. (HPCA), Feb. 2004.

10. B. Black, M. Annavaram, N. Brekelbaum, J. Devale, L.Jiang, G. H. Loh, D. Mccauley, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, C. Webb, "Die Stacking (3D) Microarchitecture", Proc. of 39th Int'l Symposium on Microarchitecture (MICRO), December 2006

11. A. Lungu, P. Bose, D. Sorin, S. German and G. Janssen. "Multicore Power Management: Ensuring Robustness via Early-Stage Formal Verification." Proc. 7th ACM-IEEE Int’l. Conference on Formal Methods and Models for Codesign (MEMOCODE), July 2009.

12. D. Gizopoulos, M. Psarakis, S. V. Adve, P. Ramachandran, S.K.S. Hari, D. Sorin, A. Meixner, A. Biswas, and X. Vera. "Architectures for Online Error Detection and Recovery in Multicore Processors." To appear in Design, Automation & Test in Europe (DATE), March 2011.

13. Anita Lungu and Daniel J. Sorin. "Verification-Aware Microprocessor Design." Proc. 16th Int’l. Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007.

14. D.H. Albonesi, R. Balasubramonian, S.G. Dropsho, S. Dwarkadas, E.G. Friedman, M.C. Huang, V. Kursun, G. Magklis, M.L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P.W. Cook, and S.E. Schuster, Dynamically Tuning Processor Resources with Adaptive Processing, IEEE Computer, Special Issue on Power-Aware Computing, Vol. 36, No. 12, pp. 49-58, December 2003.

15. Z. Wu, M. Xie and H. Hwang, Energy attack on server systems. Proc. 5th USENIX Workshop on Offensive Technologies (WOOT), 2011.

16. S. Govindavajhala and A. W. Appel, “Using memory errors to attack a virtual machine,” IEEE Symp. on Security and Privacy, May 2003.

17. P. Dadvar and K. Skadron, “Potential thermal security risks in,” 21st IEEE Semi-Therm Symp., 2005.

18. P. Bose, A. Buyuktosunoglu, J. A. Darringer, M. S. Gupta, M. B. Healy, H. Jacobson, I. Nair, J. A. Rivers, J. Shin, A. Vega, A. J. Weger, “Power management of multi-core chips: challenges and pitfalls,” Proc. Design Automation and Test in Europe (DATE), March 2012.

19. S. Sethumadhavan et al. Tutorial on Hardware Security, ISCA 2011.

20. M. Floyd, M. Ware, K. Rajamani, T. Gloekler, B. Brock, P. Bose, A. Buyuktosunoglu, J. Rubio, B. Schubert, B. Spruth, J. Tierno, L. Pesantez. Adaptive Energy Management Features of the IBM POWER7 Chip. IBM Journal of Research and Development, Vol. 55, May/June 2011.

 

Organizer Bios:

Alper Buyuktosunoglu received PhD degree in electrical and computer engineering from University of Rochester. Currently, he is a Research Staff Member in Reliability and Power-Aware Microarchitecture department at IBM T. J. Watson Research Center. He has been involved in research and development work in support of IBM p-series and z-series microprocessors in the areas of power-aware computer architectures, dynamic power management and high-level power modeling. His research interests are in the areas of high performance, low-power, complexity-aware computer architectures, and power-performance modeling of microprocessors. He has over 35 pending/issued patents, has received several IBM-internal awards, has published over 45 papers, and has served on various conference technical program committees in these areas. Dr. Buyuktosunoglu is a senior member of the IEEE and is currently serving on the editorial board of IEEE MICRO. His most recent conference tutorial speaker experiences were at ISCA-2008, ISCA-2011 and MICRO-2009.

Pradip Bose is a Research Staff Member and Manager of the Reliability- and Power-Aware Microarchitecture department at IBM T. J. Watson Research Center at Yorktown Heights, NY. He has been with IBM Research for over 27 years and has been involved in the architecture definition and associated pre-silicon modeling of the full range of IBM POWER-series microprocessors, beginning with the pioneering RISC super scalar research project in the early eighties. Pradip has a Ph.D from University of Illinois at Urbana-Champaign and is the author or co-author of over 80 peer-reviewed publications. He holds the title of “Master Inventor” within IBM in recognition of his patent portfolio, and is also a member of the IBM Academy of Technology. He has been actively involved in various IEEE/ACM conference committees and is the past editor-in-chief of IEEE Micro. He has given numerous past tutorials at conferences: ISCA, MICRO, HPCA, Sigmetrics, ICS, VLSI Design, VLSI Test Symposium, International Test Conference, etc. He is a Fellow of IEEE and a Senior Member of ACM.