Monday June 8, 2009

20-001

08:30-08:45

Welcome

08:45-10:15

 Session I

Davis, Krishna, Ramani, Derby, Vu

A Proposal for Efficient CPU-Accelerator Handshake

 

Beltran, Martorell, Torres, Ayguadé

Accelerating Software Memory Compression on the Cell/B.E.

 

Scarpazza

High-Performance, Data-parallel Document Inversion for the Cell Processor

10:15-10:30

Break

10:30-11:30

Session II

Mehdipour, Honda, Kataoka, Inoue, Murakami

An Accelerator Based on Single-Flex Quantum Circuits for a High-Performance Reconfigurable Computer

 

Van Lunteren, Rohrer, Atasu, Hagleitner

Regular Expression Acceleration at Multiple Tens of Gb/s

11:30-12:30

Panel

Accelerator Choices: Power-Performance Efficiency vs. Programmability

Li, Fu

Accelerated and Lightweight Web Management Model for Virtualization

 

Cho, Janssen, Nair, Shin

Exploring High-Level Languages for Accelerator Design

                                    

Golander, Levison

Aligning the Reliability Level Provided by Accelerators to that of General Purpose Processors

 

McDonald, Jacobs, Gutin, Zia, Liu, Kraft

Serial Code Accelerators for Heterogenous Multicores, Employing SiGe HBT BiCMOS and 3D Memory for Memory Wall Mitigation

 

Brusco, Marongiu, Palazzari

Optimizing the Matrix-Matrix Product with HCE