Application specific accelerators provide an efficient method of offloading computationally intensive task from the general purpose processor. Application specific accelerators are emerging in high performance computer architectures such as IBM’s Mainframe, Cell-based and Roadrunner supercomputer systems, SUN’s Niagara-based systems and others. The option of employing application specific accelerators brings lots of opportunities as well as challenges to the chip designer. The designer must arrive at the appropriate parts of the applications to accelerate with a hardware accelerator, design an efficient accelerator such that the hardware cost is amortized, adapt OS/compilers to make an efficient use of the hardware accelerator and so on.
This workshop brings together hardware and software researchers and practitioners for discussion on the potential and limitations of application specific accelerators in the specific context of high-end processors, servers and supercomputing systems.
The workshop focuses on characterizing, modeling, and optimizing the role of accelerators in the light of high performance computing architecture paradigms and workloads. Topics of interest include, but are not limited to:
Accelerator functionality and services
Modeling and simulation of accelerator alternatives
Implications of accelerators on compiler and OS; software exploitation of accelerator enabled architectures
Leveraging accelerators to optimize reliability/performance/power
Effect on OS scheduling and resource management with accelerators
Methods for virtualization of accelerators
Accelerator-aware general purpose processor and systems architecture
Co-processor offload versus bus-connected remote offload in accelerator enabled systems of the future
Power, performance, reliability, dependability and security in the context of accelerators
3D integration chip technology and accelerator-enabled architectures
Also, a post-workshop special issue of IEEE Micro or IEEE Computer is planned