Workshop on Quality-Aware Design (W-QUAD)

June 21, 2008
Beijing, China

To be held in conjunction with the 35th International Symposium on Computer Architecture ( ISCA 35 )

Program



Organizers:
David H. Albonesi
Cornell University
albonesi@csl.cornell.edu

Pradip Bose
IBM T. J. Watson Research Center
pbose@us.ibm.com

Alper Buyuktosunoglu
IBM T. J. Watson Research Center
alperb@us.ibm.com

Scope:
The quest for higher performance in the face of late CMOS era technological constraints, has resulted in chip/system architecture and design trends that are increasingly more complex. In addition to multiple cores, with heterogeneous accelerator sub-cores, it is common to find multithreaded execution supported by each primary core within each chip. The on-chip cache hierarchy and interconnect topologies are also increasingly more sophisticated. On- and off-chip (programmable) controllers to manage performance, power, reliability and even yield are becoming necessary to enable static and dynamic optimization across a multi-dimensional state space. The software programmability issues in multi-core chip offerings are emerging as a potentially major inhibitor to peformance and end-user quality of service, especially in systems that demand adherence to real-time response. As such, the ability to ensure design quality, delivered product quality and eventual quality of service to the end-user, have become much more challenging than in the past. Design quality is measured in terms of ease of testing, verification, development cost and achieved pre-product performance; product quality is measured in terms of in-field system reliability (availability), performance, usability (programmability), security and cost of ownership. Power and thermal efficiency dictate issues related to reliability and cost of ownership quite directly. In this workshop, we focus on research and development geared toward quality-conscious system architectural design: i.e., design paradigms and methodologies that worry about aspects of quality from the very early stages of microarchitecture definition and design.
Topics of interest include, but are not limited to: