PPoPP 2008 Schedule

WEDNESDAY
12:30 - 14:00Keynote (during lunch), Chair: Sid Chatterjee
Compilers and Parallel Computing Systems
    Frances Allen
14:00 - 14:30 Break
14:30 - 14:35 Welcome
14:35 - 16:05 Static analysis, Chair: Marc Shapiro
Automatic Data Movement and Computation Mapping for Multi-level Parallel Architectures with Explicitly Managed Memories (slides )
   Muthu Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J Ramanujam, Atanas Rountev and P Sadayappan
Type Inference for Locality Analysis of Distributed Data Structures (slides )
   Satish Chandra, Vijay Saraswat, Vivek Sarkar and Rastislav Bodik
Quasi-Static Scheduling for Safe Futures
   Armand Navabi, Xiangyu Zhang and Suresh Jagannanthan
16:05 - 17:00Break and poster set-up
17:00 - 19:00Poster session, with refreshments
THURSDAY
7:45 - 8:30 Continental breakfast
8:30 - 9:30 Parallel algorithms, Chair: Greg Bronevetsky
Scalable Packet Classification Using Interpreting -- A Cross-platform Multi-core Solution (slides )
    Haipeng Cheng, Zheng Chen, Bei Hua and Xinan Tang
FastForward for Efficient Pipeline Parallelism: A Cache-Optimized Concurrent Lock-Free Queue (slides )
    John Giacomoni, Tipp Moseley and Manish Vachharajani
9:30 - 10:30 Matrix product for special platforms, Chair: Jeff Vetter
Matrix Product on Heterogeneous Master-Worker Platforms (slides )
    Jack Dongarra, Jean-Francois Pineau, Yves Robert and Frederic Vivien
High Performance Linear Algebra on a Spatially Distributed Processor(slides )
    Jeff Diamond, Behnam Robatmili, Steve Keckler, Robert Van de Geijn, Kazushige Goto and Doug Burger
10:30 - 11:00 Break
11:00 - 12:30 GPUs and SIMD, Chair: Tim Harris
Application Optimization and Performance Evaluation of a Multithreaded GPU Using CUDA
    Shane Ryoo, Christopher Rodrigues, Sara Baghsorkhi, Sam Stone, David Kirk and Wen- mei Hwu
Massive Parallel LDPC Decoding on GPU (slides )
    Gabriel Falc„o, Leonel Sousa and Vitor Silva
A Case Study in SIMD Text Processing with Parallel Bit Streams (slides )
    Robert D. Cameron
12:30 - 14:00Lunch
14:00 - 15:00 Programming model extensions, Chair: Lauren Smith
Performance without Pain = Productivity: Data Layouts and Collectives in UPC (slides )
    Rajesh Nishtala, George Almasi and Calin Cascaval
Programming with Tiles (slides )
    Jia Guo, Ganesh Bikshandi, Basilio Fraguela, Maria Garzaran and David Padua
15:00 - 15:30 Break
15:30 - 17:30 Runtime systems, Chair: Liviu Iftode
SuperMatrix: A Multithreaded Runtime Scheduling System for Algorithms-by-Blocks (slides )
    Ernie Chan, Field G. Van Zee, Paolo Bientinesi, Enrique S. Quintana-Orti, Gregorio Quintana-Orti and Robert van de Geijn
Design and Implementation of a High-Performance MPI for C# and the Common Language Infrastructure (slides )
    Douglas Gregor and Andrew Lumsdaine
A Portable Runtime Interface For Multi-Level Memory Hierarchies (slides )
    Mike Houston, Ji-Young Park, Manman Ren, Timothy Knight, Kayvon Fatahalian, Alex Aiken, William Dally and Pat Hanrahan
ZOID: I/O-Forwarding Infrastructure for Petascale Architectures (slides )
    Kamil Iskra, John W. Romein, Kazutomo Yoshii and Pete Beckman
17:30 - 18:00 Break
18:00 - 19:30 Banquet
FRIDAY
7:45 - 8:30 Continental breakfast
8:30 - 10:00 Formal aspects of transactions and speculation, Chair: Philippas Tsigas
Nested Parallelism in Transactional Memory (slides )
    Kunal Agrawal, Jeremy Fineman and Jim Sukha
On the Correctness of Transactional Memory (slides )
    Rachid Guerraoui and Michal Kapalka
Modeling Optimistic Concurrency via Quantitative Dependence Analysis (slides )
    Christoph von Praun, Rajesh Bordawekar and Calin Cascaval
10:00 - 10:30Break
10:30 - 12:30 Panel: "Where Will All the Threads Come From?"
Moderator:John Mellor-Crummey, Rice University
Panelists:John Feo, Microsoft
Sanjeev Kumar, Intel
Bradley Kuszmaul, MIT
Jan-Willem Maessen, Sun Microsystems
Keshav Pingali, University of Texas at Austin
Vivek Sarkar, Rice University
Slides
12:30 - 14:00 Lunch
14:00 - 15:30 Transactional memory I, Chair: Maged Michael
Split Hardware Transaction: True Nesting of Transactions Using Best-effort Hardware Transactional Memory (slides )
    Yossi Lev and Jan-Willem Maessen
Transactional Boosting: A Methodology for Highly-Concurrent Transactional Objects (slides )
    Maurice Herlihy and Eric Koskinen
Concurrent GC Leveraging Transactional Memory (slides )
    Phil McGachey, Ali-Reza Adl-Tabatabai, Richard L. Hudson, Vijay Menon, Bratin Saha and Tatiana Shpeisman
15:30 - 16:00 Break
16:00 - 17:30 Transactional memory II: STM implementation, Chair: Bratin Saha
Toward High Performance Nonblocking Software Transactional Memory (slides )
    Virendra Marathe and Mark Moir
Dynamic Performance Tuning of Word-Based Software Transactional Memory (slides )
    Pascal Felber, Torvald Riegel and Christof Fetzer
Software Transactional Memory for Large-Scale Clusters (slides )
    Robert Bocchino, Vikram Adve and Bradford Chamberlain
17:30 - 17:45 Best paper presentation and closing remarks

A PDF copy of the program is available here.