LCPC2006: Preliminary Program
10:00-10:30 - Coffee Break
10:30-12:00 - Session 2: Programming Models
Can Transactions Enhance Parallel Programs?
[Full paper]
[Slides]
Troy A. Johnson, Sang-Ik Lee, Seung-Jai Min and Rudolf Eigenmann
Design and Use of htalib -- a Library for Hierarchically Tiled Arrays
[Full paper]
[Slides]
Ganesh Bikshandi, Jia Guo, Christoph von Praun, Gabriel Tanase, Basilio B. Fraguela, Maria J. Garzaran, David Padua and Lawrence Rauchwerger
SP@CE - An SP-based Programming Model for Consumer Electronics Streaming Applications
[Full paper]
[Slides]
Ana Lucia Varbanescu, Maik Nijhuis, Arturo Gonzalez Escribano, Henk Sips, Herbert Bos and Henri Bal
12:00-13:00 - Lunch
13:00-15:00 - Session 3: Code generation
Chair: Peng Wu, IBM Research
Data Pipeline Optimization for Shared Memory Multiple-SIMD Architecture
[Full paper]
Weihua Zhang, Tao Bao, Binyu Zang and Chuanqi Zhu
Dependence-based Code Generation for a CELL Processor
[Full paper]
[Slides]
Yuan Zhao and Ken Kennedy
Expression and Loop Libraries for High-Performance Code Synthesis
[Full paper]
Christopher Mueller and Andrew Lumsdaine
Specializing Code for FFT libraries
[Full paper]
[Slides]
Minhaj KHAN and Henri-Pierre CHARLES
15:00-15:30 - Coffee Break
15:30-17:00 - Session 4: Parallelism
A Characterization of Shared Data Access Patterns in UPC Programs
[Full paper]
[Slides]
Christopher Barton, Calin Cascaval and Jose Amaral
Exploiting Speculative Thread-Level Parallelism in Data Compression Applications
[Full paper]
[Slides]
Shengyue Wang, Antonia Zhai and Pen-Chung Yew
On Control Signals for Multidimensional Time
[Full paper]
[Slides]
DaeGon Kim, Gautam Gupta and Sanjay Rajopadhye
10:00-10:30 - Coffee Break
10:30-12:00 - Session 6: Compilation Techniques
An Effective Heuristic for Simple Offset Assignment with Variable Coalescing
[Full paper]
[Slides]
Hassan Salamy and J. (Ram) Ramanujam
Iterative Compilation by Exploration of Kernel Decomposition
[Full paper]
[Slides]
Denis Barthou, Sebastien Donadio, Alexandre Duchateau, William Jalby and Eric Courtois
Quantifying Uncertainty in Points-To Relations
[Full paper]
[Slides]
Constantino Ribeiro and Marcelo Cintra
12:00-13:00 - Lunch
13:00-14:30 - Session 7: Data Structures
Cache Behavior Modelling for Codes Involving Banded Matrices
[Full paper]
[Slides]
Diego Andrade, Basilio B. Fraguela and Ramón Doallo
Tree-Traversal Orientation Analysis
[Full paper]
[Slides]
Kevin Andrusky, Stephen Curial and Jose Nelson Amaral
UTS: An Unbalanced Tree Search Benchmark
[Full paper]
[Slides]
Stephen Olivier, Jun Huan, Jinze Liu, Jan Prins, James Dinan, P. Sadayappan and Chau-Wen Tseng
14:30-15:00 - Coffee Break
15:00-17:00 - Session 8: Register Allocation
Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files
[Full paper]
[Slides]
Jenq-Kuen Lee, Sheng-Yuan Chen and Chung-Ju Wu
Optimal Bitwise Register Allocation using Integer Linear Programming
[Full paper]
[Slides]
Rajkishore Barik, Christian Grothoff, Rahul Gupta, Vinayaka Pandit and Raghavendra Udupa
Register Allocation: What does the NP-Completeness Proof of Chaitin et al. Really Prove?
[Full paper]
[Slides]
Florent Bouchez, Alain Darte, Christophe Guillon and Fabrice Rastello
19:00-21:00 - Banquet
Guest speaker: Dr. Frederica Darema, Senior Science and Technology Advisor, National Science Foundation
[Slides]
9:00-11:00 - Session 9: Memory Management
Chair: Rudolf Eigenmann, Purdue University
Custom Memory Allocation for Free
[Full paper]
[Slides]
Alin Jula and Lawrence Rauchwerger
Optimizing the use of static buffers for DMA on a CELL chip
[Full paper]
Tong Chen, Zehra Sura, Kathryn O'Brien and Kevin O'Brien
Runtime Address Space Computation for SDSM Systems
[Full paper]
[Slides]
Jairo Balart, Marc Gonzalez, Xavier Martorell, Eduard Ayguade and Jesus Labarta
Static Heap Analysis for Automatic Parallelization
[Full paper]
[Slides]
Mark Marron, Deepak Kapur, Darko Stefanovic and Manuel Hermenegildo
11:00-12:00 - Closing Remarks