A multidisciplinary group of Berkeley researchers met for 18 months to discuss this change. Our investigations into the future opportunities in led to the follow recommendations which are more revolutionary what industry plans to do:
Phil Colella identified 7 numerical methods that he believed will be important for science and engineering for at least next decade. The idea is that programs that implement these numerical methods may change, but the methods themselves will remain important. After examining how well these "7 dwarfs" of high performance computing capture the computation and communication of a much broader range of computing-- including embedded computing, computer graphics and games, data bases, and machine learning--we doubled them yielding "14 dwarfs." Those interested in our perspective on parallelism should take a look at the wiki: http://view.eecs.berkeley.edu.
To rapidly evaluate all the possible alternatives in parallel architectures and programming systems, we need a flexible, scalable, and economical platform that is fast enough to run extensive applications and operating systems.
Today, one to two dozen processor cores can be programmed into a single FPGA. With multiple FPGAs on a board and multiple boards in a system, 1000 processor architectures can be explored. Such a system will not just invigorate multiprocessors research in the architecture community, but since processors cores can run at 100 to 200 MHz, a large scale multiprocessor would be fast enough to run operating systems and large programs at speeds sufficient to support software research. Hence, we believe such a system will accelerate research across all the fields that touch multiple processors: operating systems, compilers, debuggers, programming languages, scientific libraries, and so on. Thus the acronym RAMP, for Research Accelerator for Multiple Processors.
A group of 10 investigators from 6 universities (Berkeley, CMU, MIT, Stanford Texas Washington) have volunteered to create th RAMP "gateware" (logic to go into the FPGAs) and have the boards fabricated and available at cost . It will run industrial standard instruction sets (Power, SPARC, ...) and operating systems (Linux, Solaris, ...) We hope to have a system that can scale to 1000 processors in late 2007 that costs universities about $100 per processor. I'll report on our results for the initial RAMP implementations at the meeting. Those interested learning more should take a look at: http://view.eecs.berkeley.edu
His work was recognized by education and research awards from ACM (Karlstrom Educator Award, Fellow) and IEEE (Von Neumann Medal, Mulligan Educator Medal, Johnson Information Storage Award, Fellow) and by election to the National Academy of Engineering. In 2005 he shared Japan's Computer & Communication awards with Hennessy and was named to the Silicon Valley Engineering Hall of Fame. This year he received the Distinguished Service Award from CRA and was elected to both the American Academy of Arts and Sciences and to the National Academy of Sciences.