| WEDNESDAY | |
|---|---|
| 8:45 - 9:00 | Welcome |
| 9:00 - 10:00 | Keynote:
Compiler Research in the 21st
Century David Padua, University of Illinois at Urbana-Champaign |
| 10:00 - 10:45 | Break |
| 10:45 - 12:45 | Multicores |
| A Source-to-Source Transformation Infrastructure for
Multicore Architectures | |
| Runtime Support for Enabling Data-Intensive
Applications on Cluster of Multi-Cores | |
| A Kernel-Based Intermediate Representation for
Automatic Parallelization on Multi-Core Systems | |
| Performance of OSCAR Multigrain Parallelizing
Compiler on Multicore Processors | |
| 12:45 - 13:45 | Lunch |
| 13:45 - 15:15 | Library Generators |
| Automatic Parallelization of Models using Pipeline
Extraction from Combined RHS and Inlined Solvers | |
| Generating Parallel Libraries for Linear Transforms
of General Input Size | |
| Strategies for Exploiting the GPU Memory Hierarchy
for FFT | |
| 15:15 - 15:45 | Break |
| 15:45 - 17:15 | Optimization |
| Simulation of the Lattice QCD and Technological
Trends in Computation | |
| A Global Approach For MPEG-4 AVC Encoder
Optimization | |
| Invited Talk: Revisiting Out-of-SSA
Translation for Correctness, Efficiency, and Speed | |
| THURSDAY | 9:00 - 10:00 | Keynote: Portable Parallel Programs Thomas Gross, ETH Zürich |
| 10:00 - 10:45 | Break |
| 10:45 - 12:45 | Programming for Cell |
| Programming models for the Cell/B.E. processor - an
overview with examples | |
| FFT Program Generation for the Cell BE | |
| Optimized Mapping of Pipelined Task Graphs on the
Cell BE | |
| Compiling Effectively for Cell with GCC | |
| 12:45 - 13:45 | Lunch |
| 13:45 - 15:45 | Parallel Programming Models |
| Invited Talk: Auto-parallelisation using
dynamic analysis and machine learning | |
| New Abstractions for Data Parallel Programming | |
| Programming and Debugging Shared Memory Programs with
the Data Coloring | |
| Multi-core Implementations of the Concurrent
Collections Programming Model | |
| 17:00 - 21:00 | Social Event |
| FRIDAY | |
| 9:00 - 10:30 | Performance Characterization |
| Architectural Characterization of SPEC
CPU2000 and CPU2006 on IA-64 Platform | |
| Performance Study of Non-Blocking Caches for Embedded
VLIW Processors | |
| Compiling Data-Parallel SaC for the MicroGrid
Architecture | |
| 10:30 - 11:15 | Break |
| 11:15 - 12:45 | Compiler Transformations |
| An Unified Parallel C Compiler that Implements
Automatic Communication Aggregation | |
| Specifying Loop Transformations for C2uTC
Source-to-Source Compiler | |
| Expression Rematerialization for VLIW DSP Processors
with Distributed Register File | |
| 12:45 - 13:45 | Lunch |
| 13:45 - 15:15 | Performance Tuning |
| A Feedback-Directed Approach to Performance
Improvement | |
| Detecting High-Level Performance Properties based on
Static and Dynamic Information | |
| A Polyhedral Framework for Automatic Parallelization
and Locality Optimization |